Recently, a variety of different types of electric equipment such as mobile phones, digital cameras, personal computers and so on have been widely developed. Such electric equipment commonly includes a secondary battery that supplies power to the electric equipment because the secondary battery can be used repeatedly by recharging using a charge-up circuit.
FIG. 1 is a circuit diagram of a known charge-up circuit. In FIG. 1, the charge-up circuit includes a current-to-voltage conversion circuit 101, a charge-up current control circuit 102, a reference voltage generator 103, a PMOS transistor 104, a resistor Rsen, and a secondary battery 120. The resistor Rsen is used for detecting a charge-up current ichg to the secondary battery 120. The current-to-voltage conversion circuit 101 generates and outputs a charge-up-current monitor voltage CCMON by converting the charge-up current ichg flowing through the resistor Rsen to a voltage. The charge-up current control circuit 102 controls the PMOS transistor 104 so that the charge-up-current monitor voltage CCMON becomes a predetermined reference voltage CCREF.
The current-to-voltage conversion circuit 101 includes a differential amplifier 111 and resistors R101 and R102. Generally, the differential amplifier 111 has an input offset. Accordingly, an offset adjustment mechanism is employed to eliminate the input offset of the differential amplifier 111 so as to generate the charge-up-current monitor voltage CCMON accurately for the charge-up current ichg flowing through the resistor Rsen.
FIG. 2 is a circuit diagram of the differential amplifier 111 of FIG. 1. In FIG. 2, the differential amplifier 111 includes NMOS transistors M111 and M112, PMOS transistors M113 and M114, resistors R111 and R112 for trimming, and a current source 113. The NMOS transistors M111 and M112 form a differential pair of the differential amplifier 111. Similarly, the PMOS transistors M113 and M114 also form a differential pair. Each resistor R111 and R112 is connected in series between the corresponding NMOS transistor M111 and M112 and the current source 113, respectively. The differential amplifier 111 is adjusted by trimming of the resistors R111 and R112 so as to eliminate the input offset.
However, when an input offset adjustment is performed for the above-described differential amplifier 111, fluctuation of 0.5 mv in the input offset of the differential amplifier 111 may be generated due to variation in trimming accuracy. When a fluctuation of 0.5 mv in the input offset of the differential amplifier 111 is generated, the charge-up current ichg deviates by 1/(2×rsen)mA where the resistance of the resistor Rsen is rsen, indicating that the charge-up current ichg deviates by 5 mA when the resistance rsen=0.1Ω. Thus, it is difficult to achieve further reduction of the fluctuation in the charge-up current ichg.